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data transition at first reg is sampled into reg2 then reg3 ...etc. This is latency issue and you the designer will know that. The tool does not change latency as it is vital for functionality.
Any routing/logic delays between registers is absorbed into the sampling periods.(normally 1 period unless multicycle > 1)
so what you want is [pin-to reg1 delay + number of regs in chain x clock period + last reg to pin delay]. =~ number of reg x clock period
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Yes, kaz, I absolutely agree with you! I just thought that there is a command to find out that value automatically without manual calculation.
Thank you very much!
Honored Contributor
