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As also stated in that doc you linked to:
tCO is meant to be time from clock edge at clock pin input (that clocks the output register) to data transition at output pin of that register(if its input changes). You don't need to sum up clock cycles on any other registers (that is latency)
tCO is not used for combinatorial paths. It = clock delay from pin to register + register micro tCO + register to pin delay
So I do feel it is what you are after.
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Hi kaz!
Yes, exactly, as about tCO parameter it is what you wrote. I was interested if there is such parameter that sum tCO and integrated clock cycles on other register (a path from input pin to output pin with intermediate registers inside the path).
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