--- Quote Start ---
Well, it is not exactly what I needed because my task was to find out total amount of delay from input pin to output pin in system like in example I added in the beginning of the thread (
https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/wp/wp_stxtco.pdf). But I think it only works for a combinational path, if there are more than one register in the path we need to manually sum clock cycles to Tco of output register.
--- Quote End ---
As also stated in that doc you linked to:
tCO is meant to be time from clock edge at clock pin input (that clocks the output register) to data transition at output pin of that register(if its input changes). You don't need to sum up clock cycles on any other registers (that is latency)
tCO is not used for combinatorial paths. It = clock delay from pin to register + register micro tCO + register to pin delay
So I do feel it is what you are after.
Honored Contributor
