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Hi kaz!
Yes, exactly, as about tCO parameter it is what you wrote. I was interested if there is such parameter that sum tCO and integrated clock cycles on other register (a path from input pin to output pin with intermediate registers inside the path).
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data transition at first reg is sampled into reg2 then reg3 ...etc. This is latency issue and you the designer will know that. The tool does not change latency as it is vital for functionality.
Any routing/logic delays between registers is absorbed into the sampling periods.(normally 1 period unless multicycle > 1)
so what you want is [pin-to reg1 delay + number of regs in chain x clock period + last reg to pin delay]. =~ number of reg x clock period
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