How to disable lvds output in arria 10 chip dynamically?

Hi FvM,

Thanks for your help.

I found that there's one required choice (Use pseudo-differential buffer) in altera gpio ip. So if I use SSTL IO standard instead of POD io standard, there's no error, right?

BRs,

Lambert

Hi, Aqid

I tried this solution, and I found that when I set the oe to low, there's no data on the bus. I used two diff pair to do this test. I found that there's one pad which input has random 0->1 or 1-> 0 toggle, and anothe didn't have when these two pad are all input and diff bus was not driven. I don't know why, could you help proide some information for this?

my design: arria 10 (10ax115n3f45i2sg)

one diff pair : (in 2j bank, which use the reference clock from its dedicated clk pin)

pll instance1();

gpio instance1(); (simple register mode)

another diff pair: (in 2h bank, which use the reference clock from its dedicated clk pin)

pll instance2();

gpio instance2(); (simple register mode)

pattern : 0101010...

connection : these two diff pairs connected directly.

BRs,

Lambert

Hi, FvM

Now I am just for testing one differential pair could used be either input or output when use bus lvds solution. And now just we have limited hardware resource, we connect two differential pairs to test the solution. And we didn't setup the external termination part (without series terminations). So I think your opinion is reasonable (arbitary data (= noise)). Thanks!

BRs,

Lambert

Hi, Aqid

Sorry for the delayed response.

Current I think bus lvds solution is okay for our design. We will test again when we get the newest hardware design. Thanks.

BRs,

Lambert