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ContributorHow to disable lvds output in arria 10 chip dynamically?
LVDS IO-standard has no tri-state feature, independent of FPGA series or Quartus version. You can refer to BLVDS (bus LVDS) if it's fast enough. On Arria 10, there's no BLVDS choice available, you'll use differential SSTL instead.
Super ContributorHi,
not sure what you are trying to achieve. Seeing no output with OE=0 (output inactive) is expectable. A receiver on the bus might however read arbitary data (= noise) when no peer is driving the bus. You can try bias resistors as used in RS-485 to enforce a defined state of undriven bus.
ContributorHi, FvM
Now I am just for testing one differential pair could used be either input or output when use bus lvds solution. And now just we have limited hardware resource, we connect two differential pairs to test the solution. And we didn't setup the external termination part (without series terminations). So I think your opinion is reasonable (arbitary data (= noise)). Thanks!
BRs,
Lambert
