Forum Discussion
lambert_yu
Contributor
ContributorHow to disable lvds output in arria 10 chip dynamically?
Hi, all fpga: arria 10 quartus II: 18.0 standard I have requirement for the lvds ip, when I have no data output, I need to disable lvds pin dynamically. So I add below design: tx_ser...
LVDS IO-standard has no tri-state feature, independent of FPGA series or Quartus version. You can refer to BLVDS (bus LVDS) if it's fast enough. On Arria 10, there's no BLVDS choice available, you'll use differential SSTL instead.
AqidAyman_Altera
Regular Contributor
Regular ContributorHi Lambert,
Do you have any update on what being asked by @FvM?
Do you still need help on this?
Regards,
Aqid
lambert_yuContributor
ContributorHi, Aqid
Sorry for the delayed response.
Current I think bus lvds solution is okay for our design. We will test again when we get the newest hardware design. Thanks.
BRs,
Lambert
