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ContributorHow to disable lvds output in arria 10 chip dynamically?
LVDS IO-standard has no tri-state feature, independent of FPGA series or Quartus version. You can refer to BLVDS (bus LVDS) if it's fast enough. On Arria 10, there's no BLVDS choice available, you'll use differential SSTL instead.
Regular ContributorBased on the Application note, you can use Differential SSTL-I8 Class I and II if you want to implement BLVDS interface. With the BLVDS, the output buffer and input buffer can share with the same I/O pins, and you need OE signal to disable the LVDS output buffer when not sending signals.
lambert_yuHi, Aqid
I tried this solution, and I found that when I set the oe to low, there's no data on the bus. I used two diff pair to do this test. I found that there's one pad which input has random 0->1 or 1-> 0 toggle, and anothe didn't have when these two pad are all input and diff bus was not driven. I don't know why, could you help proide some information for this?
my design: arria 10 (10ax115n3f45i2sg)
one diff pair : (in 2j bank, which use the reference clock from its dedicated clk pin)
pll instance1();
gpio instance1(); (simple register mode)
another diff pair: (in 2h bank, which use the reference clock from its dedicated clk pin)
pll instance2();
gpio instance2(); (simple register mode)
pattern : 0101010...
connection : these two diff pairs connected directly.
BRs,
Lambert
