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Contributor

1 year ago

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How to disable lvds output in arria 10 chip dynamically?

Hi, all fpga: arria 10 quartus II: 18.0 standard I have requirement for the lvds ip, when I have no data output, I need to disable lvds pin dynamically. So I add below design: tx_ser...

Generic Io

Programmable Logic Device

FvM
1 year ago
LVDS IO-standard has no tri-state feature, independent of FPGA series or Quartus version. You can refer to BLVDS (bus LVDS) if it's fast enough. On Arria 10, there's no BLVDS choice available, you'll use differential SSTL instead.
See: https://www.intel.com/content/www/us/en/docs/programmable/683803/current/implementing-bus-lvds-interface-in-supported.html

FvM

Super Contributor

1 year ago

LVDS IO-standard has no tri-state feature, independent of FPGA series or Quartus version. You can refer to BLVDS (bus LVDS) if it's fast enough. On Arria 10, there's no BLVDS choice available, you'll use differential SSTL instead.

See: https://www.intel.com/content/www/us/en/docs/programmable/683803/current/implementing-bus-lvds-interface-in-supported.html

lambert_yu

Contributor

1 year ago

Hi FvM,

Thanks for your help.

I found that there's one required choice (Use pseudo-differential buffer) in altera gpio ip. So if I use SSTL IO standard instead of POD io standard, there's no error, right?

BRs,

Lambert

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How to disable lvds output in arria 10 chip dynamically?

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