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Altera_Forum
Honored Contributor
Honored ContributorHow to delay in verilog HDL ?
How to delay in verilog HDL in designing?
13 Replies
Altera_Forumyeah i understand that ... when i post this comment , i didnt see that post due to browser pblem ..
Thnx alot ..- Altera_Forum
rbugalho already answered you.
What didn't you understand ? - Altera_Forum
yeah same pblm i m facing :(... please tell me how is it possible to provide delay in hardware if we implement it to FPGA ...
- Altera_Forum
It depends on your purpose.
Often, what you want to do can be achieved with a counter. Another common technique is to use shift registers to delay signals. You can also add (small, 1 to 20 ns maybe and not very accurate) propagation delays by setting min/max delays constraints in TimeQuest. - Altera_Forum
thank you for your reply ,
But am using FPGA so do you know how can i add delay to the output ?? - Altera_Forum
yes, that will work in simulation.
But it does not work in hardware (FPGA). - Altera_Forum
hello , i want to add delay to an output in verilog language ,
hazard is the "output signal" can i use this way ??? if ( result_ns < vt ) # 5000000 hazard = 1; else # 5000000 hazard = 0; thanks - Altera_Forum
Suppose this situation:
the device is MAX7000, and the inputs are trigger signal, the pulses on each trigger are random and continuous. How to implement delay 100 to 3000ns like this? - Altera_Forum
用标志（使能）控制计数器。
标志为0，计数器开始计数xxx时间，标志置一； 标志为1，计数器清零。 Use the flag(enable flag) to control counter. When the flag is 0, the counter begin to count some long time, set the flag as the time is up. When the flag is 1, clear the counter. - Altera_Forum--- Quote Start --- Indeed what delay? but intersting to discuss... delay type 1 : low level things like TCO, gate delays etc. delay type 2 : one or (n) clock latency of design delay type 3 : of a function output valid relevant to input delay type 4 : fractional sample delay(of a signal) others : of postings or payments ...etc. --- Quote End --- Would using count down timer be the best in all these instances well in parrticular type 2?
