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Honored Contributor
Honored ContributorHow to delay in verilog HDL ?
How to delay in verilog HDL in designing?
Altera_ForumHonored Contributor
Honored ContributorSuppose this situation:
the device is MAX7000, and the inputs are trigger signal, the pulses on each trigger are random and continuous. How to implement delay 100 to 3000ns like this?
