Altera_Forum
Honored Contributor
Honored ContributorHow to delay in verilog HDL ?
How to delay in verilog HDL in designing?
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Altera_ForumHonored Contributor
Honored Contributorhello , i want to add delay to an output in verilog language ,
hazard is the "output signal" can i use this way ??? if ( result_ns < vt ) # 5000000 hazard = 1; else # 5000000 hazard = 0; thanks
