Altera_Forum
Honored Contributor
Honored ContributorHow to delay in verilog HDL ?
How to delay in verilog HDL in designing?
Forum Discussion
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Indeed what delay? but intersting to discuss... delay type 1 : low level things like TCO, gate delays etc. delay type 2 : one or (n) clock latency of design delay type 3 : of a function output valid relevant to input delay type 4 : fractional sample delay(of a signal) others : of postings or payments ...etc. --- Quote End --- Would using count down timer be the best in all these instances well in parrticular type 2?
