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Honored Contributor
Honored ContributorHow to delay in verilog HDL ?
How to delay in verilog HDL in designing?
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Altera_ForumHonored Contributor
Honored Contributor用标志（使能）控制计数器。
标志为0，计数器开始计数xxx时间，标志置一； 标志为1，计数器清零。 Use the flag(enable flag) to control counter. When the flag is 0, the counter begin to count some long time, set the flag as the time is up. When the flag is 1, clear the counter.
