How to check clocks using SignalTap II Logic Analyzer?

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Ok, so you should see something that looks like a square wave then.

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Yes, I see square wave for any any signal except the external input clock.

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You won't see that with SignalTap. You need a scope for that sort of visualization.

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I have tried this with Oscilloscope today, and I found that there was no signal coming out from SMA connectors (only noise). I checked again the board schematic and reference manual. I am not so sure but it looks like I can only drive the reference clocks (dedicated for XCVR channels) out of the board, but not the clock from core.

One point I am still confused. I am trying to have a synchronous global system clock that is used for managing and reconfigurating local MAC, PHY, traffic controller components basically. Is this necessary to have this synced when building the dual-board communication? Otherwise, the transceiver reference clock, 156.25 MHz, is used for both Ethernet TX and RX to work. My wonder is should I just make this reference clock synced or I need also to have the system clock synced? Can you help to give an advice?

Thanks again.

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I have tried this with Oscilloscope today, and I found that there was no signal coming out from SMA connectors (only noise). I checked again the board schematic and reference manual. I am not so sure but it looks like I can only drive the reference clocks (dedicated for XCVR channels) out of the board, but not the clock from core.

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If an SMA goes to a REFCLK, that is an input path, not an output.

Look on page 11 of the schematic, there are two SMA connectors, IO_CLKOUT1 and IO_CLKOUT2. Page 25 shows where they come from; PLLT1CKO0p/n.

Those pins sound like they are a PLL output ... is that what you are using?

What about page 9, J18, it comes from U21 (ICS557-03). That should be a clock signal too. I'd recommend using this one, since it will not accumulate PLL jitter from the FPGA.

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One point I am still confused. I am trying to have a synchronous global system clock that is used for managing and reconfigurating local MAC, PHY, traffic controller components basically. Is this necessary to have this synced when building the dual-board communication? Otherwise, the transceiver reference clock, 156.25 MHz, is used for both Ethernet TX and RX to work. My wonder is should I just make this reference clock synced or I need also to have the system clock synced? Can you help to give an advice?

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Its up to how you want to deploy your system;

1) Synchronous clocks

Can be used when you are using the transceivers for custom applications, where you do not have the option to 'bit-slip' to accommodate differences in frequencies between oscillators on different boards.

2) Asynchronous clocks (of the same frequency)

This is what most networks use. The clocks on the boards are nominally the same frequency, but they are not exactly. The protocol used over the wire has some 'slack' built in, and the transmit or receive sides have FIFOs for matching data rates. The protocols involve bit-sequences that can be stuffed into the transceiver link, or deleted, as needed to match overall data rates.

(1) is simpler to deal with when you are trying to figure stuff out.

Cheers,

Dave

Thanks a lot for your time and very detailed support.

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Look on page 11 of the schematic, there are two SMA connectors, IO_CLKOUT1 and IO_CLKOUT2. Page 25 shows where they come from; PLLT1CKO0p/n.

Those pins sound like they are a PLL output ... is that what you are using?

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Exactly I am using these pins (J16, J17). Yes, the IO_CLKOUT1/2 come from FPGA pin (M20,L20). So I tried to assign a clock output signal to these pins. What I did is as follows:

1. At transmitter side:

input S4GT_CLK1;

//assign S4GT_CLK1 to pin (K34,J34), generated by U21, a 25-MHz oscillator //and spread spectrum clock buffer circuitry, freq is set by rotating DIP Switch //Pin-Out SW2

output IO_CLKOUT1;

assign IO_CLKOUT1 = S4GT_CLK1;

//assign IO_CLKOUT1 to pin (M20,L20)

2. Connect SMA cables from (J16->J14), (J17->J15)

3. At receiver side:

input S4GT_EXT_CLK5;

//assign S4GT_EXT_CLK5 to pin (AV22, AW22)

input LOCAL_S4GT_CLK1;

//assign LOCAL_S4GT_CLK1 to pin (K34,J34)

4. Check S4GT_EXT_CLK5, LOCAL_S4GT_CLK1 with SigntalTap and Oscilloscope

And S4GT_EXT_CLK5 is just noise in Scope and looks strange in SignalTap.

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What about page 9, J18, it comes from U21 (ICS557-03). That should be a clock signal too. I'd recommend using this one, since it will not accumulate PLL jitter from the FPGA.

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J18 is a SMA output of the S4GT_CLK1 (U21, freq is set by rotating SW2). Whenever the board is on, we have the clock output from J18. Also I have checked this clock signal and it is nice in both Scope and SignalTap.

But in case we use this, my wonder is that, the S4GT_CLK1 is a differential clock source at the TX. But when we drive it out from J18, we have only one cable. Given that RX also need a pair of clock signal from SMA pin (J16,J17), how can we feed the two connectors with only J18? Do I need something to make a clock to differential clock or I just use either connector of the pairs?

Thanks again.

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1. At transmitter side:

input S4GT_CLK1;

//assign S4GT_CLK1 to pin (K34,J34), generated by U21, a 25-MHz oscillator //and spread spectrum clock buffer circuitry, freq is set by rotating DIP Switch //Pin-Out SW2

output IO_CLKOUT1;

assign IO_CLKOUT1 = S4GT_CLK1;

//assign IO_CLKOUT1 to pin (M20,L20)

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I don't see anything wrong with your connections.

What was the I/O standard you assigned to IO_CLKOUT1?

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J18 is a SMA output of the S4GT_CLK1 (U21, freq is set by rotating SW2). Whenever the board is on, we have the clock output from J18. Also I have checked this clock signal and it is nice in both Scope and SignalTap.

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So use this one then.

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But in case we use this, my wonder is that, the S4GT_CLK1 is a differential clock source at the TX. But when we drive it out from J18, we have only one cable. Given that RX also need a pair of clock signal from SMA pin (J16,J17), how can we feed the two connectors with only J18? Do I need something to make a clock to differential clock or I just use either connector of the pairs?

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You just need to determine whether or not you violate any input voltage specifications.

For example, note how page 11 has 50-ohm terminations to ground for S4GT_EXT_CLK5 and they lead directly to the FPGA clock pins. You can probably configure one of those signals as a single-ended clock, and then directly connect the single-ended output on J18 to the SMA J14.

Just make sure that the voltage swing of the J18 output does not violate the voltage swing on the FPGA input. Check with a scope for reflections. If things look ugly, put a 50-ohm source termination on J18 before you attach the SMA cable. It'll drop the voltage by half.

Because the S4GT_EXT_CLK5 will be routed differentially, there will be some switching noise coupled onto the N of the differential pair. But its terminated in 50-ohms to ground, and you're not using the N input at the FPGA, so that'll be fine.

Cheers,

Dave

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What was the I/O standard you assigned to IO_CLKOUT1?

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The I/O standard is 2.5V.

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You can probably configure one of those signals as a single-ended clock, and then directly connect the single-ended output on J18 to the SMA J14.

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How can I do this?

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Check with a scope for reflections. If things look ugly, put a 50-ohm source termination on J18 before you attach the SMA cable. It'll drop the voltage by half.

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How to put the source termination on the J18? Sorry, I am not an electronic guy so this basic stuff is also new to me.

Well, I just think of driving out the reference clock from one of the three generators dedicated to XCVR blocks (100, 644.25, 706.53Mhz). These are differential clocks and we can drive those to J16, J17. Especially, the clock 100Mhz can be used for system clock instead of using S4GT_CLK1 (U21). How do you think about this?

Thanks.

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The I/O standard is 2.5V.

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That is not a differential standard. If you were assigning a single-ended standard to the output clock P+N signal and using them as a differential signal, then the difference would be nothing. However, you mentioned you looked with a scope, so you would have noticed that :)

To define the input clock as single-ended, just assign it as an input with 2.5V LVCMOS logic level, or 3.3V logic level, whatever is appropriate for that I/O bank (check the schematic to ensure you use the right setting).

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How to put the source termination on the J18? Sorry, I am not an electronic guy so this basic stuff is also new to me.

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Put a 50-ohm resistor in series with the cable. Either chop up a cable, or buy a series termination. Minicircuits might have something (though you might only find end-terminations). Ignore this for now.

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Well, I just think of driving out the reference clock from one of the three generators dedicated to XCVR blocks (100, 644.25, 706.53Mhz). These are differential clocks and we can drive those to J16, J17. Especially, the clock 100Mhz can be used for system clock instead of using S4GT_CLK1 (U21). How do you think about this?

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Any time you drive a clock out of the FPGA, you will increase the jitter. However, sure, any of these schemes should work. In fact all of them should. But first, you need to get just one to work :)

Cheers,

Dave

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To define the input clock as single-ended, just assign it as an input with 2.5V LVCMOS logic level, or 3.3V logic level, whatever is appropriate for that I/O bank (check the schematic to ensure you use the right setting).

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I can only fine 3.3V LVCMOS but not 2.5V LVCMOS in the list. Also, besides 3.3V LVCMOS, level 3.3V LVTTL is usable for single-ended signal?

Thanks

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Just make sure that the voltage swing of the J18 output does not violate the voltage swing on the FPGA input.

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In case we violate the limited voltage, if Quartus recognizes and stop with an error?

and what is the worst case if we misassign the I/O standard for pins?

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I can only fine 3.3V LVCMOS but not 2.5V LVCMOS in the list. Also, besides 3.3V LVCMOS, level 3.3V LVTTL is usable for single-ended signal?

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Before you care what Quartus allows you to do, you should first check what has physically been implemented.

p11 S4GT_EXT_CLK5P/N J14/15 route to p23 AV22/AW22 which are clock inputs on Bank 3C. Page 27 shows the power. Bank 3C is connected to 2.5V.

With that knowledge, the only valid Quartus settings are LVDS or 2.5V LVCMOS.

In the case of using this pin for a single-ended input, it should allow you to select 2.5V LVCMOS.

Your comments are too vague; what list (where in Quartus) and for what pins?

Cheers,

Dave

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In case we violate the limited voltage, if Quartus recognizes and stop with an error?

and what is the worst case if we misassign the I/O standard for pins?

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If you violate the input voltage, you will damage the input clock pin on your expensive board, and it (that pin, and perhaps others) will never work again.

Check the signals with an oscilloscope before you plug them in!!

Quartus will not protect you.

Cheers,

Dave