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1. At transmitter side:
input S4GT_CLK1;
//assign S4GT_CLK1 to pin (K34,J34), generated by U21, a 25-MHz oscillator //and spread spectrum clock buffer circuitry, freq is set by rotating DIP Switch //Pin-Out SW2
output IO_CLKOUT1;
assign IO_CLKOUT1 = S4GT_CLK1;
//assign IO_CLKOUT1 to pin (M20,L20)
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I don't see anything wrong with your connections.
What was the I/O standard you assigned to IO_CLKOUT1?
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J18 is a SMA output of the S4GT_CLK1 (U21, freq is set by rotating SW2). Whenever the board is on, we have the clock output from J18. Also I have checked this clock signal and it is nice in both Scope and SignalTap.
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So use this one then.
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But in case we use this, my wonder is that, the S4GT_CLK1 is a differential clock source at the TX. But when we drive it out from J18, we have only one cable. Given that RX also need a pair of clock signal from SMA pin (J16,J17), how can we feed the two connectors with only J18? Do I need something to make a clock to differential clock or I just use either connector of the pairs?
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You just need to determine whether or not you violate any input voltage specifications.
For example, note how page 11 has 50-ohm terminations to ground for S4GT_EXT_CLK5 and they lead directly to the FPGA clock pins. You can probably configure one of those signals as a single-ended clock, and then directly connect the single-ended output on J18 to the SMA J14.
Just make sure that the voltage swing of the J18 output does not violate the voltage swing on the FPGA input. Check with a scope for reflections. If things look ugly, put a 50-ohm source termination on J18 before you attach the SMA cable. It'll drop the voltage by half.
Because the S4GT_EXT_CLK5 will be routed differentially, there will be some switching noise coupled onto the N of the differential pair. But its terminated in 50-ohms to ground, and you're not using the N input at the FPGA, so that'll be fine.
Cheers,
Dave
Honored Contributor
