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Altera_Forum
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14 years ago

How to check clocks using SignalTap II Logic Analyzer?

Hi all, I am learning how to use Signaltap II logic analyzer using this tutorial: http://www.altera.com/literature/hb/qts/qts_qii53009.pdf?gsa_pos=1&wt.oss_r=1&wt.oss=design%20debugging%20...
Altera_Forum's avatar
Altera_Forum
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14 years ago

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To define the input clock as single-ended, just assign it as an input with 2.5V LVCMOS logic level, or 3.3V logic level, whatever is appropriate for that I/O bank (check the schematic to ensure you use the right setting).

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I can only fine 3.3V LVCMOS but not 2.5V LVCMOS in the list. Also, besides 3.3V LVCMOS, level 3.3V LVTTL is usable for single-ended signal?

Thanks