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The I/O standard is 2.5V.
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That is not a differential standard. If you were assigning a single-ended standard to the output clock P+N signal
and using them as a differential signal, then the difference would be nothing. However, you mentioned you looked with a scope, so you would have noticed that :)
To define the input clock as single-ended, just assign it as an input with 2.5V LVCMOS logic level, or 3.3V logic level, whatever is appropriate for that I/O bank (check the schematic to ensure you use the right setting).
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How to put the source termination on the J18? Sorry, I am not an electronic guy so this basic stuff is also new to me.
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Put a 50-ohm resistor in series with the cable. Either chop up a cable, or buy a series termination. Minicircuits might have something (though you might only find end-terminations). Ignore this for now.
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Well, I just think of driving out the reference clock from one of the three generators dedicated to XCVR blocks (100, 644.25, 706.53Mhz). These are differential clocks and we can drive those to J16, J17. Especially, the clock 100Mhz can be used for system clock instead of using S4GT_CLK1 (U21). How do you think about this?
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Any time you drive a clock out of the FPGA, you will increase the jitter. However, sure, any of these schemes should work. In fact all of them should. But first, you need to get just one to work :)
Cheers,
Dave
Honored Contributor
