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Honored ContributorHow to check clocks using SignalTap II Logic Analyzer?
Hi all, I am learning how to use Signaltap II logic analyzer using this tutorial: http://www.altera.com/literature/hb/qts/qts_qii53009.pdf?gsa_pos=1&wt.oss_r=1&wt.oss=design%20debugging%20...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I can only fine 3.3V LVCMOS but not 2.5V LVCMOS in the list. Also, besides 3.3V LVCMOS, level 3.3V LVTTL is usable for single-ended signal? --- Quote End --- Before you care what Quartus allows you to do, you should first check what has physically been implemented. p11 S4GT_EXT_CLK5P/N J14/15 route to p23 AV22/AW22 which are clock inputs on Bank 3C. Page 27 shows the power. Bank 3C is connected to 2.5V. With that knowledge, the only valid Quartus settings are LVDS or 2.5V LVCMOS. In the case of using this pin for a single-ended input, it should allow you to select 2.5V LVCMOS. Your comments are too vague; what list (where in Quartus) and for what pins? Cheers, Dave
