Honored Contributor
Honored ContributorThanks a lot for your time and very detailed support.
--- Quote Start --- Look on page 11 of the schematic, there are two SMA connectors, IO_CLKOUT1 and IO_CLKOUT2. Page 25 shows where they come from; PLLT1CKO0p/n. Those pins sound like they are a PLL output ... is that what you are using? --- Quote End --- Exactly I am using these pins (J16, J17). Yes, the IO_CLKOUT1/2 come from FPGA pin (M20,L20). So I tried to assign a clock output signal to these pins. What I did is as follows: 1. At transmitter side: input S4GT_CLK1; //assign S4GT_CLK1 to pin (K34,J34), generated by U21, a 25-MHz oscillator //and spread spectrum clock buffer circuitry, freq is set by rotating DIP Switch //Pin-Out SW2 output IO_CLKOUT1; assign IO_CLKOUT1 = S4GT_CLK1; //assign IO_CLKOUT1 to pin (M20,L20) 2. Connect SMA cables from (J16->J14), (J17->J15) 3. At receiver side: input S4GT_EXT_CLK5; //assign S4GT_EXT_CLK5 to pin (AV22, AW22) input LOCAL_S4GT_CLK1; //assign LOCAL_S4GT_CLK1 to pin (K34,J34) 4. Check S4GT_EXT_CLK5, LOCAL_S4GT_CLK1 with SigntalTap and Oscilloscope And S4GT_EXT_CLK5 is just noise in Scope and looks strange in SignalTap. --- Quote Start --- What about page 9, J18, it comes from U21 (ICS557-03). That should be a clock signal too. I'd recommend using this one, since it will not accumulate PLL jitter from the FPGA. --- Quote End --- J18 is a SMA output of the S4GT_CLK1 (U21, freq is set by rotating SW2). Whenever the board is on, we have the clock output from J18. Also I have checked this clock signal and it is nice in both Scope and SignalTap. But in case we use this, my wonder is that, the S4GT_CLK1 is a differential clock source at the TX. But when we drive it out from J18, we have only one cable. Given that RX also need a pair of clock signal from SMA pin (J16,J17), how can we feed the two connectors with only J18? Do I need something to make a clock to differential clock or I just use either connector of the pairs? Thanks again.
