Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

How to check clocks using SignalTap II Logic Analyzer?

Hi all, I am learning how to use Signaltap II logic analyzer using this tutorial: http://www.altera.com/literature/hb/qts/qts_qii53009.pdf?gsa_pos=1&wt.oss_r=1&wt.oss=design%20debugging%20...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

--- Quote Start ---

Just make sure that the voltage swing of the J18 output does not violate the voltage swing on the FPGA input.

--- Quote End ---

In case we violate the limited voltage, if Quartus recognizes and stop with an error?

and what is the worst case if we misassign the I/O standard for pins?