how to assign clock on a dedicated path

Hi all,

I am experiencing clock skews of +3ns in the input to reg path and a skew of -3ns in reg to output path.

I got an answer from altera forum only to route the clock through a dedicated pin commonly known as global clock buffer and global clock net.

Now the question is how can i determine this particular net and pin on a family i am using. I checked the data sheet for stratix V and it doesnt have any pin named as global clock ..yes it does have [27:0] clkp and clkn and if i assign clk to these pins the results are unchanged and one more thing that the clk pin was assigned by quartus only so it assigned it to a 11clkp but the question of this global clock remains unanswered and i too have limited knowledge about it.

I am attaching the report illustrating the clock skew and the clock path.

Some information regarding the reports are that incase of +clock skew of around 3ns the slack was +ve of around 0.6 and incase of -ve clock skews the slack was -ve around -4.3.

I am working at 225 Mhz ie 4.444 clock .

So any comments will be helpfull.