how to assign clock on a dedicated path

When the clock drives a clock tree, the main advantage is that it is low-skew, and hence hits all the registers at approximately the same time. The actual delay though can be quite large. Say roughly 3-4ns(device and speed grade dependent). For an output I/O, a long clock tree hurts the setup analysis(think Tco) and helps the hold analysis(think Min Tco). For an input it does the opposite, helping the setup analysis(think Tsu) and hurting hold analysis. So where you want the clock to be is dependent on your I/O specs. If you have tight Tco requirements, then you want the clock path to be as short as possible. If you have tight Tsu requirements on the inputs, then you want it to be longer. Hold plays in the opposite.

Just adding a PLL will compensate for the clock tree. This makes the clock path shorter. By itself, this can be a good thing or a bad thing, depending on the situation(although more often than not it's a good thing).

The PLL also lets you phase-shift the clock. So on top of shortening it, you can phase-shift it wherever you want. So let's say you really wanted it long, you could just phase-shift the clock forwared by 3ns and get back to where you started.

Finally, and this is important, the PLL makes the clock tree Process, Voltage, and Temp(PVT) calibrated. So, let's say you start with a 4ns global clock tree, and that is a good value for your design. That would be 4ns in the slow corner, but it might be 2ns in the fast timing corner. So your clock tree varies between 2-4ns over PVT. That's 2ns of margin that is completely lost because you can't account for it.

Now add a PLL. Your clock delay might now drop to 0.5ns(I'm not going into how a PLL does that). Plus, it's PVT compensated, so it will stay at 0.5ns. So let's say you really wanted the original 4ns shift, so you manually add another 3.5ns shift to your PLL, getting you back to 4ns. With the PLL, it will be 4ns at both the slow and fast corners, so you don't lose 2ns of margin to PVT.