how to assign clock on a dedicated path

I just replied to your earlier post, as to why clock skew is normal. One thing in your first screen shot, CLKCTRL_G4 means it's on a global, the 4th one. Also, it's driving an M20K, so if this is an input path, the timing won't be good. (An input pin to a M20K is going to have a long data delay).

For outputs, the launch clock path in the FPGA will hurt setup time, as it takes longer to get your data out, but helps hold time(for the same reason). For inputs, the long clock delay helps setup, since it latches the clock later in time, but hurts hold. Also, I would strongly recommend a PLL at those speeds. 225Mhz for I/O timing is pretty fast. Do-able, but fast.