how to assign clock on a dedicated path

Nothing wrong with an M20K on an internal path.

Most users don't spend too much time on I/O analysis when looking at a sub-module. Note that your clock skew is going to disappear when it's hooked into the full design, because the other side it hooks up to will probably be fed by the same clock. So your constraints would have to account for this. There are just a lot of things that can't fully be taken into account, and so they usually work on everything but the I/O of the sub-module, and then when it's hooked together, they see what doesn't work. (They don't completely ignore the I/O boundaries of a sub-module. Register wherever you can so that it won't have long delays to/from the next module, or at least keep the logic as short as possible.) But I think you're spending too much time on that, when you'll be able to analyze it much better later on. If everything within each module meets timing with some margin, the interfaces will most likely(hopefully) not be too difficult.