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Altera_Forum's avatar
Altera_Forum
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14 years ago

how to assign clock on a dedicated path

Hi all, I am experiencing clock skews of +3ns in the input to reg path and a skew of -3ns in reg to output path. I got an answer from altera forum only to route the clock through a dedicated...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Ok ok ...now I got you...Using a PLL will give me control over the skew and how much i want it to be shifted ..offcourse that 0.5ns margin is natural and also not in my control so i can phase shift my clock according to the requirements for inputs and outputs..

Thanks :)