how to assign clock on a dedicated path

Ok you mean my inputs and outputs should be registered. And yes one thing i forgot to mention that this is a module level analysis its not the integrated system level..Its a single block and i am doing analysis of that.

You earlier guided me to make the outputs as virtual inorder to remove output buffers .

Well the output timing was solved with some constraints and removing the buffers.

The data delays as seen is around 4.6ns from input to reg where the IC delays are around 3ns for each and every input to reg path.

If i remove the input buffers the IC delays are increasing and accounting for even worse data delays.

The reason might be that at module level the module is scattered all over the FPGA and hence accounting for large IC delays .

Can I contrain the IC delays (I know I am deviating from the thread topic but also know in the next thread i will have the answer from you :)).