Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorhow to assign clock on a dedicated path
Hi all, I am experiencing clock skews of +3ns in the input to reg path and a skew of -3ns in reg to output path. I got an answer from altera forum only to route the clock through a dedicated...
Altera_ForumHonored Contributor
Honored ContributorYou only showed the clock going to the M20K(data required path). If the data arrival path is from an input port, then it will be a long data delay because the M20Ks are inside the die, not in the IO cell like a register is. So you'll have a long data delay. Generally that makes timing more difficult. You would most likely want to have a register on your inputs and outputs.
