How can I generate a reset signal?

Obviously, the power-on self-reset is only meaningful for systems that don't have a reset input. I completely agree, that a reset input is the preferred way. If you don't have it, you can force the power on condition also by reloading the FPGA through JTAG, a straightforward and simple method in my opinion.

On the other hand, if the system has a reset input, you should care that power-on (or reconfigure) condition is also triggering the same behaviour as reset. Otherwise, you may need to cycle the power in debugging, although you provided a reset ...

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That's not generally true, I think. The design can work based on the defined power-on reset feature. As clarified in the Quartus Software Manual, all core registers have a power-on reset value of 0. In the original design, Quartus is performing some optimizations, also involving register polarity inversions. By specifying an explicite power-up value in the reg definition, this optimization is canceled and cnt starts at 0

reg cnt = 4'd0;

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Hi FvM,

I didn't want to say this will not work for FPGA's, but I would never do it in this way.

When you debug your design and it hangs, you only can bring the design in defined state by switching off the power. Then you to reprogramm the FPGA .....

I think it is not a recommented way at least in the debugging stage of a project.

Kind regards

GPK

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The Quartus will stick reset to vcc

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That's not generally true, I think. The design can work based on the defined power-on reset feature. As clarified in the Quartus Software Manual, all core registers have a power-on reset value of 0. In the original design, Quartus is performing some optimizations, also involving register polarity inversions. By specifying an explicite power-up value in the reg definition, this optimization is canceled and cnt starts at 0

reg cnt = 4'd0;

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Many IC need a reset signal to initialation, but when I write codes in FPGA, the Quartus will stick the signal to a fixed level, the code is as below:

input clk;

output reset;

reg reset;

reg[3:0] cnt;

always @ (posedge clk)

begin

if(cnt<10)

begin reset<=0;cnt<=cnt+1; end

else

begin reset<=1; end

end

The Quartus will stick reset to vcc, who can help me how to generate a reset signal? Thanks very much!

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Hi,

the behaviour of your counter is only predictable if we assume that after power-up all registers will have a defined state. I would re-write the code a little bit:

module reset (clk, reset,reset_int );

input clk;

input reset;

output reset_int;

reg reset_int;

reg[3:0] cnt;

always @ (posedge clk)

begin

if (reset)

begin

cnt <= 0;

reset_int <= 1;

end

else if(cnt<10)

begin

reset_int <=0;

cnt<=cnt+1;

end

else

begin

reset_int <=1;

end

end

endmodule

You need an input reset signal in order to bring your design (also your reset generator) in a defined state. In our example the counter would run only one time after power up and your pulse length depends on how the registers a powered up. Worst case you will never get an reset pulse. I don't know how the power-up sequence of the FPGA's lookslike, but would never write a design which depends on it.

I have a small Quartus Project attached.

Kind regards

GPK

I posted a reset controller here:

http://www.alteraforums.com/forum/attachment.php?attachmentid=1393&d=1250716848

Your code looks fine except your polarities are inverted on your reset. Should be:

input clk;
output reset;
reg reset;
reg cnt;
always @ (posedge clk)
    if(cnt<10) begin
        reset  <=0;
        cnt     <=cnt+1;
    end else
        reset  <=1;

Jake