How can I generate a reset signal?

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The Quartus will stick reset to vcc

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That's not generally true, I think. The design can work based on the defined power-on reset feature. As clarified in the Quartus Software Manual, all core registers have a power-on reset value of 0. In the original design, Quartus is performing some optimizations, also involving register polarity inversions. By specifying an explicite power-up value in the reg definition, this optimization is canceled and cnt starts at 0

reg cnt = 4'd0;