How can I generate a reset signal?

Obviously, the power-on self-reset is only meaningful for systems that don't have a reset input. I completely agree, that a reset input is the preferred way. If you don't have it, you can force the power on condition also by reloading the FPGA through JTAG, a straightforward and simple method in my opinion.

On the other hand, if the system has a reset input, you should care that power-on (or reconfigure) condition is also triggering the same behaviour as reset. Otherwise, you may need to cycle the power in debugging, although you provided a reset ...