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Many IC need a reset signal to initialation, but when I write codes in FPGA, the Quartus will stick the signal to a fixed level, the code is as below:
input clk;
output reset;
reg reset;
reg[3:0] cnt;
always @ (posedge clk)
begin
if(cnt<10)
begin reset<=0;cnt<=cnt+1; end
else
begin reset<=1; end
end
The Quartus will stick reset to vcc, who can help me how to generate a reset signal? Thanks very much!
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Hi,
the behaviour of your counter is only predictable if we assume that after power-up all registers will have a defined state. I would re-write the code a little bit:
module reset (clk, reset,reset_int );
input clk;
input reset;
output reset_int;
reg reset_int;
reg[3:0] cnt;
always @ (posedge clk)
begin
if (reset)
begin
cnt <= 0;
reset_int <= 1;
end
else if(cnt<10)
begin
reset_int <=0;
cnt<=cnt+1;
end
else
begin
reset_int <=1;
end
end
endmodule
You need an input reset signal in order to bring your design (also your reset generator) in a defined state. In our example the counter would run only one time after power up and your pulse length depends on how the registers a powered up. Worst case you will never get an reset pulse. I don't know how the power-up sequence of the FPGA's lookslike, but would never write a design which depends on it.
I have a small Quartus Project attached.
Kind regards
GPK
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