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Honored Contributor
Honored ContributorHow can I generate a reset signal?
Many IC need a reset signal to initialation, but when I write codes in FPGA, the Quartus will stick the signal to a fixed level, the code is as below: input clk; output reset; reg reset;...
Altera_ForumHonored Contributor
Honored ContributorI posted a reset controller here:
http://www.alteraforums.com/forum/attachment.php?attachmentid=1393&d=1250716848 Your code looks fine except your polarities are inverted on your reset. Should be:input clk;
output reset;
reg reset;
reg cnt;
always @ (posedge clk)
if(cnt<10) begin
reset <=0;
cnt <=cnt+1;
end else
reset <=1;
