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That's not generally true, I think. The design can work based on the defined power-on reset feature. As clarified in the Quartus Software Manual, all core registers have a power-on reset value of 0. In the original design, Quartus is performing some optimizations, also involving register polarity inversions. By specifying an explicite power-up value in the reg definition, this optimization is canceled and cnt starts at 0
reg cnt = 4'd0;
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Hi FvM,
I didn't want to say this will not work for FPGA's, but I would never do it in this way.
When you debug your design and it hangs, you only can bring the design in defined state by switching off the power. Then you to reprogramm the FPGA .....
I think it is not a recommented way at least in the debugging stage of a project.
Kind regards
GPK
Honored Contributor
