High bandwidth data transfer between hps and fpga

Here is the design that I was referring to:

https://www.altera.com/support/support-resources/design-examples/soc/fpga-to-hps-bridges-design-example.html

There are examples for both Cyclone V and Arria 10. It focuses on the high bandwidth F2H and F2S bridges. Hope this will help

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Here is the design that I was referring to:

https://www.altera.com/support/support-resources/design-examples/soc/fpga-to-hps-bridges-design-example.html

There are examples for both Cyclone V and Arria 10. It focuses on the high bandwidth F2H and F2S bridges. Hope this will help

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Hi sunshine,

Thanks for the reference link, but I can't compile the fpga project to make the output file .sof compatible with my kit. Beside, the hps_system.qsys is missing 3 subcomponents: AXI_cache_security and custom_reset_synchronizer_50, custom_reset_synchronizer_fast.

Could you give me some advice to make it work? I'm expecting to transfer data between FPGA and linux application with bandwidth >= 60MB/s ~ 480Mb/s and I wonder whether this example can reach this requirement

I'm using DE1-SOC kit and Quartus 15.0.

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Hi sunshine,

Thanks for the reference link, but I can't compile the fpga project to make the output file .sof compatible with my kit. Beside, the hps_system.qsys is missing 3 subcomponents: AXI_cache_security and custom_reset_synchronizer_50, custom_reset_synchronizer_fast.

Could you give me some advice to make it work? I'm expecting to transfer data between FPGA and linux application with bandwidth >= 60MB/s ~ 480Mb/s and I wonder whether this example can reach this requirement

I'm using DE1-SOC kit and Quartus 15.0.

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You'll need to Open Qsys and generate the HDL files first. After that, then you can compile the design

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As a general rule of thumb the highest speed method of moving data between the FPGA and HPS is to use the FPGA-to-SDRAM interface. If you require the FPGA to have access to cacheable data then that's the exception to the rule and you would use the F2H bridge (and a master in the FPGA) instead. I would stay away from moving data between the FPGA and HPS using the MPU or DMA inside the HPS which is why that design sunshine pointed to doesn't bother to implement it.

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I have followed the example which sunshine recommended and make my system works as:

1. Load my data in FPGA layer to a FIFO

2. Using msgDMA to transfer data from the fifo to a sdram port, lightweight h2f bridge is used to control msgdma only.

3. In my linux application, I read the data from sdram using mmap and it worked well.

However, there is some troubles

1. The read data from sdram will be processed with some heavy works such as applying filter, image processing, and using TCP/IP to transfer the processed data to other host PC. All the heavy works make my kit slow down and effect to the sampling frequency of my data in fpga.

Therefore, I'm thinking of transferring my data directly from the sdram to ethernet using the HPS EMAC controller and my question is how do I configure some parameters of TCPIP socket as the host IP address, port, etc. I'm expecting to achieve highest bandwidth as high as possible.

2. My flow is too complicated now,

data(fpga) --> fifo --> dma --> sdram --> dma --> ethernet emac --> TCPIP--> host PC.

but it's the easiest flow I can merge from multiple examples on the internet. Could you give me some advice to simple the flow?

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I have followed the example which sunshine recommended and make my system works as:

1. Load my data in FPGA layer to a FIFO

2. Using msgDMA to transfer data from the fifo to a sdram port, lightweight h2f bridge is used to control msgdma only.

3. In my linux application, I read the data from sdram using mmap and it worked well.

However, there is some troubles

1. The read data from sdram will be processed with some heavy works such as applying filter, image processing, and using TCP/IP to transfer the processed data to other host PC. All the heavy works make my kit slow down and effect to the sampling frequency of my data in fpga.

Therefore, I'm thinking of transferring my data directly from the sdram to ethernet using the HPS EMAC controller and my question is how do I configure some parameters of TCPIP socket as the host IP address, port, etc. I'm expecting to achieve highest bandwidth as high as possible.

2. My flow is too complicated now,

data(fpga) --> fifo --> dma --> sdram --> dma --> ethernet emac --> TCPIP--> host PC.

but it's the easiest flow I can merge from multiple examples on the internet. Could you give me some advice to simple the flow?

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Hello,

we have implemented "High-Bandwidth" data transfer using the sdram to Ethernet-method with Cyclone V SoC. The data flow is data(fpga)->sdram->HPS EMAC -> TCP/IP -> Host PC. We get about 200 Mbit/s throughput with this method. The bottleneck of this method is the Sdram-controller's maximum clock speed which is 300-367 MHz (dependig on the device's speed grade). So this method would maybe not work for you if want to get at least 480 Mbit/s throughput.

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Hello,

we have implemented "High-Bandwidth" data transfer using the sdram to Ethernet-method with Cyclone V SoC. The data flow is data(fpga)->sdram->HPS EMAC -> TCP/IP -> Host PC. We get about 200 Mbit/s throughput with this method. The bottleneck of this method is the Sdram-controller's maximum clock speed which is 300-367 MHz (dependig on the device's speed grade). So this method would maybe not work for you if want to get at least 480 Mbit/s throughput.

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Thanks for reminding. It seems like my flow currently, but I wanna give it a try. :confused:

How do you configure the flow from sdram to TCP/IP? Where can I configure the IP address, port for socket? Could you share some ideas to implement it?

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Thanks for reminding. It seems like my flow currently, but I wanna give it a try. :confused:

How do you configure the flow from sdram to TCP/IP? Where can I configure the IP address, port for socket? Could you share some ideas to implement it?

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I'm not a software guy, so I cannot give any detailed advice on this. But I guess you are using Linux in your system. The ethernet settings can be configured using /etc/network/interfaces.

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I'm not a software guy, so I cannot give any detailed advice on this. But I guess you are using Linux in your system. The ethernet settings can be configured using /etc/network/interfaces.

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yeah, I'm running Linux system, but I'm thinking about other way.

I read the technical reference of Cyclone V there is a DMA controller in EMAC module so I wanna use this DMA (or an external mgsDMA is ok) to forward my data from SDRAM directly to EMAC which support Reduced Gigabit Media Independent Interface (RGMII).

If I load the data from sdram to Linux application and use Linux socket to forward to the host PC, I think this way can't give a better solution than the above.