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I have followed the example which sunshine recommended and make my system works as:
1. Load my data in FPGA layer to a FIFO
2. Using msgDMA to transfer data from the fifo to a sdram port, lightweight h2f bridge is used to control msgdma only.
3. In my linux application, I read the data from sdram using mmap and it worked well.
However, there is some troubles
1. The read data from sdram will be processed with some heavy works such as applying filter, image processing, and using TCP/IP to transfer the processed data to other host PC. All the heavy works make my kit slow down and effect to the sampling frequency of my data in fpga.
Therefore, I'm thinking of transferring my data directly from the sdram to ethernet using the HPS EMAC controller and my question is how do I configure some parameters of TCPIP socket as the host IP address, port, etc. I'm expecting to achieve highest bandwidth as high as possible.
2. My flow is too complicated now,
data(fpga) --> fifo --> dma --> sdram --> dma --> ethernet emac --> TCPIP--> host PC.
but it's the easiest flow I can merge from multiple examples on the internet. Could you give me some advice to simple the flow?
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Hello,
we have implemented "High-Bandwidth" data transfer using the sdram to Ethernet-method with Cyclone V SoC. The data flow is data(fpga)->sdram->HPS EMAC -> TCP/IP -> Host PC. We get about 200 Mbit/s throughput with this method. The bottleneck of this method is the Sdram-controller's maximum clock speed which is 300-367 MHz (dependig on the device's speed grade). So this method would maybe not work for you if want to get at least 480 Mbit/s throughput.
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