High bandwidth data transfer between hps and fpga

As a general rule of thumb the highest speed method of moving data between the FPGA and HPS is to use the FPGA-to-SDRAM interface. If you require the FPGA to have access to cacheable data then that's the exception to the rule and you would use the F2H bridge (and a master in the FPGA) instead. I would stay away from moving data between the FPGA and HPS using the MPU or DMA inside the HPS which is why that design sunshine pointed to doesn't bother to implement it.