High bandwidth data transfer between hps and fpga

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Here is the design that I was referring to:

https://www.altera.com/support/support-resources/design-examples/soc/fpga-to-hps-bridges-design-example.html

There are examples for both Cyclone V and Arria 10. It focuses on the high bandwidth F2H and F2S bridges. Hope this will help

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Hi sunshine,

Thanks for the reference link, but I can't compile the fpga project to make the output file .sof compatible with my kit. Beside, the hps_system.qsys is missing 3 subcomponents: AXI_cache_security and custom_reset_synchronizer_50, custom_reset_synchronizer_fast.

Could you give me some advice to make it work? I'm expecting to transfer data between FPGA and linux application with bandwidth >= 60MB/s ~ 480Mb/s and I wonder whether this example can reach this requirement

I'm using DE1-SOC kit and Quartus 15.0.