High bandwidth data transfer between hps and fpga

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Hi sunshine,

Thanks for the reference link, but I can't compile the fpga project to make the output file .sof compatible with my kit. Beside, the hps_system.qsys is missing 3 subcomponents: AXI_cache_security and custom_reset_synchronizer_50, custom_reset_synchronizer_fast.

Could you give me some advice to make it work? I'm expecting to transfer data between FPGA and linux application with bandwidth >= 60MB/s ~ 480Mb/s and I wonder whether this example can reach this requirement

I'm using DE1-SOC kit and Quartus 15.0.

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You'll need to Open Qsys and generate the HDL files first. After that, then you can compile the design