Honored ContributorHi,
I need to High bandwidth data transfer between hps and fpga. Which bridge should i use? I used light weight bridge but the speed of transfer data was up to 3MHz. Best Regards
Honored ContributorIf you are using Cyclone V SoC, there are FPGA-to-HPS and HPS-to-FPGA bridge that lets you select AXI width of 32, 64 or 128-bits. These bridges can accommodate larger bandwidth compared to light weight bridge.
Honored ContributorMany thak for your assistance . Is it possible to transfer data by using this bridge up to 100 MHz? how can i use this bridge ? Can you introduce me example code?
Best RegardsHonored ContributorIn this example
https://rocketboards.org/foswiki/view/projects/datamover it looks like the transfer from FPGA to HPS bridges are happening at 133MHz (multiply that with 128-bit, so 2.1GB/s assuming that the pipeline can be saturated) It you just wanted to access the HPS SDRAM and do not need coherency, you can use the FPGA-to-SDRAM bridge instead - here's an example implementation: https://rocketboards.org/foswiki/view/projects/cyclevsocsdramperformanceexampledesign Hope this helps...Honored ContributorMany thanks for your assistance. I am beginner to HPS. can you introduce me an easy example? I can not understand the role of onchip_memory and another Qsys blocks. is it better for me to start this project step by step.
Honored ContributorHi,
i used h2f_axi_master by address 0xc000000 in the linux. I this state the rate of transformating was low. What is the reason?should i use bare instead of linux?Honored ContributorThe On Chip memory in the FPGA is just a Avalon Memory component - in theory, you can replace this with another component (including your own custom component)
I'm not sure if the OS is hindering the transfer rate (could be due to various other reasons as well) - as you can see from the example above, you may want to consider using DMA in the FPGA to help speed things up. If you are letting the processor to do all the copying of the data, it may slow things down due to overheads, etc. Are you performing the transfer from HPS --> (your custom Qsys component)?Honored ContributorHi,
I transfer from HPS to FPGA IO pins. Mang thanks for your assistanceHonored ContributorSince you are connecting it to the FPGA IO, I assume that you've created a "PIO" Qsys component and connect the HPS-FPGA bridges to it. The HPS-FPGA bridge is not really efficient for such scenarios (it works better when connected to a FPGA master that requires wide data width). Perhaps it would be better to see if the FPGA IO can be controlled using IP within the FPGA, and use the HPS-FPGA lightweight bridge to update/change the registers for the FPGA IP.
Honored ContributorHi,
I do not understand your opinion? can you explain it with an example? I am trying to do it without IP. many thanksHonored ContributorThere is a design that I saw somewhere (not the Datamover) that better demonstrate the usage of the bridge. I'll try to find and post it here.
