Help with statemachine/verilog

Hello to everyone, i am having a lot of trouble to work with state machines using verilog!

module maquina_irig
    (
        clk_mi,
        rstn_mi,
        zero_mi,
        um_mi,
        p_mi,
        dez_mi,
        ts_mi,
        sinal_mi
    );
    
input clk_mi; // 20mhz from top
input rstn_mi; // reset from top
input zero_mi; // sinais irig com temporizacao
input um_mi;
input p_mi;
input dez_mi;
input ts_mi; // timestamp 
output sinal_mi; //sinal de saida
wire  ts_mi;
reg sinal_mi;
reg  current_state, next_state;
parameter idle = 0, send_p = 1, seconds =2;
             
always @ (posedge clk_mi or negedge rstn_mi)
        if (~rstn_mi)
         begin
                current_state <= idle;
         end
         else
         begin
                current_state <= next_state;
        end
        
always @ (posedge clk_mi)
    begin
        next_state = current_state;
        case (current_state)
            idle:                 next_state = send_p;
            send_p:                next_state = seconds;
            seconds:    next_state = idle;
            default:                next_state = idle;
        endcase
    end
always @ (posedge clk_mi)
    begin
        sinal_mi = 0;
        next_state = current_state;
        case (current_state)
            idle:                 ;
            send_p:                sinal_mi = p_mi;
            seconds:           ;
            default:             ;
        endcase
end
endmodule

Error (10028): Can't resolve multiple constant drivers for net "next_state" at maquina_irig.v(61)
Error (10029): Constant driver at maquina_irig.v(41)
Error (10028): Can't resolve multiple constant drivers for net "next_state" at maquina_irig.v(61)
Error (10028): Can't resolve multiple constant drivers for net "next_state" at maquina_irig.v(61)