Help with statemachine/verilog

I'm not sure if I understood what the statemachine is supposed to do but if this is just a realtime timer for keeping track of year:days:hours:minutes:seconds then I would just implement this as a bunch of modulo counters. When the 'second' counter hits 60 that enables the 'minute' counter to increment. Likewise when the 'minute' counter hits '60' you enable the 'hour' counter to increment.

With separate counters you are just implement a bunch of simple but separate state machines. This approach is much easier since the state transitions become trivial because you are not trying to encode it all into one state machine.