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Altera_Forum's avatar
Altera_Forum
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15 years ago

Help with statemachine/verilog

Hello to everyone, i am having a lot of trouble to work with state machines using verilog! here is my code module maquina_irig ( clk_mi, rstn_mi, zero_mi, ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Quartus II has a template menu option with some state machine implementations that you can look at. With a verilog or VHDL file open got to Edit --> Insert Template and choose the one you want to use.