Help with statemachine/verilog

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You apparently intend to send them sequentially. Using two states is the siimplest way..

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Yes i've done that, but now my state machine has 20 states, where 10 of them is just a replicated state

F.E

SECOND:
                begin
                    if(ts_mi==0)
                        sinal_mi <= zero_mi;
                    else if(ts_mi==1)
                        sinal_mi <= um_mi;
                end
                
            P_BEFORE_MINUTE:
                begin
                sinal_mi <= p_mi;
                end

I need to verify the bits on a byte reponsable for the seconds, then send a "p_mi" signal, and it goes like this untill years!

seconds->p_mi->minuts->p_mi->hours-> ....... ->years

All the p_before (minute/hour..etc) has the same code

Same applies for the hour/minut etc..

.. Is there some way to do a simplification?

Thanks for the support