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Altera_Forum's avatar
Altera_Forum
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15 years ago

Help with statemachine/verilog

Hello to everyone, i am having a lot of trouble to work with state machines using verilog! here is my code module maquina_irig ( clk_mi, rstn_mi, zero_mi, ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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Quartus II has a template menu option with some state machine implementations that you can look at. With a verilog or VHDL file open got to Edit --> Insert Template and choose the one you want to use.

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Thanks for the tip. I am using the Moore state machine now.

My output is a 1bit reg.

I want to send in one state two signals, "1" and "0" in the same state

How can i do that? I can't just do

Initial_State:

begin

out<= 1;

out<= 0;

end

right?

Thanks..