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Altera_Forum
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15 years ago

Help with statemachine/verilog

Hello to everyone, i am having a lot of trouble to work with state machines using verilog! here is my code module maquina_irig ( clk_mi, rstn_mi, zero_mi, ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Actually i have my counters that generate my timestamp and i am using my it to generate an IRIG-B signal

this time machinal is to generate the irig-b signal. Is a little bit more complex than simple counters and my boss told me to do using state machines :D

It's working now throught.. Thanks a lot for the support!