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Altera_Forum
Honored Contributor
Honored ContributorHelp with statemachine/verilog
Hello to everyone, i am having a lot of trouble to work with state machines using verilog! here is my code
module maquina_irig
(
clk_mi,
rstn_mi,
zero_mi,
...
Altera_ForumHonored Contributor
Honored ContributorThe error is caused by simple violation of Verilog syntax
