Help with statemachine/verilog

The error is caused by simple violation of Verilog syntax. You can't drive the variable next_state in more than one place.

But it's completely unclear, why you did it all. Apparently you have copied second always block without thinking. The assignment next_state = current_state; in the third always block is simply useless.

In addition, assigning both next_state and current_state in an edge sensitive always block is far from a reasonable FSM design. It causes an unwanted delay of one clock cycle and possibly strange behaviour. I suggest to use FSM examples from a Verilog text book as astarting point.