Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Handling large amount of Data between modules in Verilog

Hi all,

I want to handle large amounts of data between Modules.

I somehow need to connect up to 1024 inputs and 1024 outputs which are [16:0] width each. For the moment, the only solution which came to my mind is the following: 


input       inp_fre_0;
...
input       inp_fre_1023;
output       out_fre_0;
...
output       out_fre_1023;
However, it appears to me that this is not the ideal solution and somehow bad style.

For registers, Verilog offers packed array registers 


reg      rex_fim_X1;
Is there anything similar for Inputs and Outputs? Quartus says that there is something similar available in SystemVerilog. However i don't wanna start with this since I'm still having enough trouble with Verilog itself...

Is there maybe an even better way to do the data handling besides using inputs and outputs?

A little inspiration (and a short code sample :)) would really be appreciated.

Cheers,

Jonas

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    I'm not a Verilog expert (not even close as I use VHDL for about five years now, after using AHDL for over 10 years) but I checked Thomas & Moorby's 'The Verilog Hardware Description Language' and looking into a MegaWizard generated .v file, I feel it should work like this 

    module ttt (
	inp_fre  ,
	... ,
	... ) ;
	input	  inp_fre;
   ...
endmodule
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    System Verilog brings also structurized data types (e.g. arrays) for module interfaces, but standard Verilog hasn't it. So you have to represent the connection by a large [17*1024-1..0] "flattened" vector. But that's no problem for the design compiler, bad readability is probably the main drawback.

    You'lll need a rather large FPGA to have about 17500 internal signals, and also a considerable amount of routing resources. Did you verify, that the design is feasible, apart from the particular module connection problem?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Alas, I tried it in Quartus II after reading FvM's post and it doesn't work. Looks like Verilog is quite limited , so stepping up to SystemVerilog seems to be the advice ... so I'll have to look for a good book on SystemVerilog

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    I tried josyb solution but wasn't able to let it work.

    How to index the internal signals that now have a double index?

    If I declare it like this:

    --- Quote Start ---

    module tmp2(A[1:0],Y);

    input [7:0]A;

    wire [7:0] A;

    output [7:0] Y;

    wire [7:0] Y;

    assign Y = A+{A,1'b1};

    endmodule

    --- Quote End ---

    it looks like A is a 2bit signal

    If I declare it like this:

    --- Quote Start ---

    module tmp2(A[7:0],Y);

    input [1:0]A;

    wire [1:0] A;

    output [7:0] Y;

    wire [7:0] Y;

    assign Y = A+{A,1'b1};

    endmodule

    --- Quote End ---

    I get an error

    Any hint?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    I essentially tried what nplttr shows before I posted my second reply.

    Looks like I'll stick to VHDL, it may be a bit verbose sometimes, but at least I don't have to paste/copy/edit two sets of 1024 lines to declare what jonas.lindmann wants. In VHDL it is as simple (at first sight) as :
     port (
...
inp_fre : in std_logic_2D(1023 downto 0 , 16 downto 0) ;
...
) ;

    or with parameters : 

    entity ttt is
  generic (
     NUM_OF_PORTS : natural := 1024 ;
     WIDTH_PORT  : natural := 17
     ) ;
   port (
     ...
     inp_fre : in std_logic_2D(NUM_OF_PORTS - 1 downto 0 , WIDTH_PORT - 1 downto 0) ;
     ....
     ) ;
end ttt ;

    It seems there is no Verilog equivalent for this? Great :eek:

    I wonder why Altera switched from AHDL to Verilog for their building blocks? It looked like they were going to switch to VHDL, which partly convinced me of VHDL too.