Handling large amount of Data between modules in Verilog

I essentially tried what nplttr shows before I posted my second reply.

Looks like I'll stick to VHDL, it may be a bit verbose sometimes, but at least I don't have to paste/copy/edit two sets of 1024 lines to declare what jonas.lindmann wants. In VHDL it is as simple (at first sight) as :

 port (
...
inp_fre : in std_logic_2D(1023 downto 0 , 16 downto 0) ;
...
) ;

or with parameters :

entity ttt is
  generic (
     NUM_OF_PORTS : natural := 1024 ;
     WIDTH_PORT  : natural := 17
     ) ;
   port (
     ...
     inp_fre : in std_logic_2D(NUM_OF_PORTS - 1 downto 0 , WIDTH_PORT - 1 downto 0) ;
     ....
     ) ;
end ttt ;

It seems there is no Verilog equivalent for this? Great :eek:

I wonder why Altera switched from AHDL to Verilog for their building blocks? It looked like they were going to switch to VHDL, which partly convinced me of VHDL too.